Heterojunction bipolar transistors and methods of manufacture

ABSTRACT

Semiconductor structures and methods of manufacture semiconductors are provided which relate to heterojunction bipolar transistors. The method includes forming two devices connected by metal wires on a same wiring level. The metal wire of a first of the two devices is formed by selectively forming a metal cap layer on copper wiring structures.

CROSS REFERENCE TO RELATED APPLICATIONS

The present application is a continuation application of co-pending U.S. patent application Ser. No. 12/539,284, filed on Aug. 11, 2009, the contents of which are incorporated by reference in its entirety herein.

FIELD OF THE INVENTION

The invention relates to semiconductor structures and methods of manufacture and, more particularly, to heterojunction bipolar transistors and methods of manufacture.

BACKGROUND

Heterojunction bipolar transistors (HBT) are used in SiGe technologies due to their high performance (Ft, Fmax) and capabilities of driving high currents. However, SiGe HBTs have scaled poorly with newer generations, due to degradation in maximum allowed current density in the Cu wiring (i.e., electromigration limits), which require the use of multiple levels of wide wires. SiGe HBT performance is also limited by the maximum current flow out of the emitter and collector.

Solutions to the electromigration issues have given rise, though, to other issues such as, for example, poor Time-Dependent Dielectric Breakdown (TDDB) lifetime, wire RC variability, and poor yield. For example, in known solutions, wiring is provided to the emitter through M1-M2 and the collector (and base) through M1, with wide wires fanning out. These types of layouts add extra contact area in which known problems can be exacerbated by self-heating and extreme use conditions of SiGe HBT chips (i.e., need to support>125° C.). In other solutions, the HBT is widened to allow for more CABAR (ContAct BAR) or card enable signal CE (bar); however, widening the HBT increases the footprint and chip cost, and also degrades device performance. Also, known solutions cause TDDB reliability problems in minimum spaces wires or in chips with large areas. Other solutions increase wire resistance (e.g., about 2× for 90 nm M1) and wire resistance variability.

Accordingly, there exists a need in the art to overcome the deficiencies and limitations described hereinabove.

SUMMARY

In a first aspect of the invention, a method comprises forming two devices connected by metal wires on a same wiring level, the metal wire of a first of the two devices being formed by selectively forming a metal cap layer on copper wiring structures. In embodiments, one of the devices is a transistor such that the selectively forming a metal cap layer on copper wiring structures comprises electrically connecting to an emitter, collector and base of a heterojuncture bipolar transistor.

In another aspect of the invention, a method of forming a semiconductor comprises: forming an emitter, base and collector of a HBT; forming a field effect transistor (FET) adjacent to the HBT; forming wiring structures in electrical connection to the FET and the emitter, base, and collector of the HBT; forming copper wiring layers in electrical connection to the wiring structures; and selectively forming a metal conductive material on the wiring structures in electrical connection of the emitter, base and collector.

In yet another aspect of the invention, a structure comprises an HBT comprising a collector, base and emitter and wiring structures in electrical connection with the collector, base and emitter. The structure further comprises a copper cap layer deposited on the wiring structures and a selective metal to copper deposited on the copper cap layer. The structure further comprises a FET adjacent to the HBT, where the FET includes a copper wiring structure devoid of the selective metal.

In another aspect of the invention, there is a design structure tangibly embodied in a machine readable medium used for designing, manufacturing, or testing an integrated circuit. The design structure includes the method steps and/or structure of the present invention.

In another aspect of the invention, a structure comprises a first device connected to a metal wire comprising a metal cap layer on copper wiring structures. The structure further comprises a second device connected to a metal wire on a same level as the metal wire of the first device. The metal wire of the second device is devoid of the metal cap layer on copper wiring structures.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS

The present invention is described in the detailed description which follows, in reference to the noted plurality of drawings by way of non-limiting examples of exemplary embodiments of the present invention.

FIGS. 1-3 show structures and respective processes in accordance with aspects of the invention;

FIGS. 4 and 5 show structures and respective processes in accordance with additional aspects of the invention;

FIG. 6 shows a graph comparing peak fT to peak Jc; and

FIG. 7 is a flow diagram of a design process used in semiconductor design, manufacture, and/or test.

DETAILED DESCRIPTION

The invention relates to semiconductor structures and methods of manufacture and, more particularly, to heterojunction bipolar transistors (HBT) and methods of manufacture. In embodiments, the present invention increases electromigration lifetime of the HBT by selectively patterning and wiring wires only in the HBT region. In more specific embodiments, the present invention comprises selectively placing capped wiring (e.g., copper wiring capped with TaN, TiN, CoWP, Sn, or other metal that improves electromigration) to the SiGe HBT high current terminals to allow for higher current density, a tighter pitch layout, and/or elimination of staggered M1 and M2 wiring. In this way, advantageously, the present invention provides increased SiGe HBT performance by maximizing current flow out of the emitter and collector region, while minimizing space requirements. Additionally, the present invention minimizes Time-Dependent Dielectric Breakdown (TDDB). The present invention also improves the performance of the HBT by locally integrating TaN, TiN, CoWP or Sn (or other metals discussed below) to the SiGe HBT without affecting other wiring on the chip.

FIG. 1 shows a starting structure 10 in accordance with an aspect of the invention (e.g., SiGe BiCMOS wafer, post M1 copper processing). The structure 10 includes an HBT region comprising a collector 14, SiGe base 16 and emitter 18, formed over a substrate 12. Wiring structures 24 a are formed in a layer of dielectric 22, and are electrically connected to the collector 14 of the HBT. Contact structures 24 b are formed in the dielectric 22, and are electrically connected to the SiGe base 16 of the HBT. A contact structure 24 c is also formed in the dielectric 22, and is electrically connected to the emitter 18 of the HBT. In embodiments, the contact structures 24 a, 24 b and 24 c can be, for example, damascene tungsten stud contacts with thin TiN liner; damascene copper stud contacts with a Ta-based liner; or dual damascene tungsten or copper contacts formed in conjunction with the damascene M1 layer 28. In embodiments, the contact structures 24 a, 24 b and 24 c are formed using conventional damascene or dual damascene lithographic, etching and deposition processes, well known to those of skill in the art such that further explanation is not required herein for an understanding of the present invention. The first wiring level (M1) 28 is formed using either copper single or dual damascene processing, with thin refractory metal liners, such as Ta-based metals, as known in the art. If the first wiring level (M1) 28 is formed with dual-damascene processking, then the contact structures 24 a, 24 b, and 24 c would be formed of dual-damascene copper.

Still referring to FIG. 1, a wiring layer 26 is formed in the dielectric 22, and is electrically connected to each of the wiring structures 24 a, 24 b and 24 c. In embodiments, the wiring layer 26 can be, for example, a damascene copper wire lined with a thin layer of refractory metal, such as TaN. In embodiments, the wiring layer 26 is formed using conventional lithographic, etching and deposition processes, well known to those of skill in the art such that further explanation is not required herein for an understanding of the present invention. The wiring layer 26 may be, for example, about 190 nm in height; although other dimensions are also contemplated by the invention. For example, the height of the wiring layer 26 may be 190 nm+/−20%.

The structure 10 further includes an optional conventional field effect transistor (FET) 20 having a dedicated wiring structure 24 d electrically connected thereto. The wiring structure 24 d is electrically connected to a wiring layer 28 and can be, for example, tungsten or titanium. The wiring structure 24 d can be, in embodiments, lined with a titanium nitride liner, and formed using conventional lithographic, etching polishing, and deposition processes. The wire layer 28 can be copper and may be, for example, about 190 nm in height; although other dimensions are also contemplated by the invention as noted above.

FIG. 2 shows an intermediate structure and respective processing steps in accordance with as aspect of the invention. In particular, a photoresist layer 30, which may include antireflective layers under and/or over as known in the art, is deposited on the structure 10 of FIG. 1. An opening is formed in the photoresist 30 over the HBT region of the structure 10 to expose the wiring layer 26. The copper portion of wiring layer 26 on each of the wiring structures 24 a, 24 b and 24 c is etched using, for example, dilute sulfuric acid/hydrogen peroxide (DSP) solution to form a trench 32 over the HBT region. The trenches 32 can be approximately 40 nm in depth; although other dimensions are also contemplated by the present invention. For example, the depth of the trenches 32 can be about 40 nm+/−10%. The wiring layer 28 in areas outside the opening in the photoresist remain protected (e.g., intact) by the mask layer during the etching process.

FIG. 3 shows a final structure and respective processing steps in accordance with an aspect of the invention. In particular, the photoresist is removed using, for example, a plasma or downstream plasma resist strip using a N₂/H₂ gas solution. In embodiments, the ambient resist is an oxygen free plasma strip which prevents corrosion of the copper layer 26. The structure can be optionally cleaned after resist strip using, for example, a Dilute Hydrofluoric Acid (DHF).

After cleaning, a metal 34 is deposited in the trenches. The metal can be, for example, TaN, TaN/Ta, Ru, W, Mn, or TiN, deposited to a height of about 60 nm; although other dimensions are contemplated by the invention depending on the depth of the trenches. The deposition process can be, for example, be preceded by an argon or reactive hydrogen sputter clean, as known in the art, and a PVD deposition process which deposits the metal 34 on the HBT high current terminals (e.g., wiring structures 24 a, 24 b and 24 c). In embodiments, the metal 34 selectively increases electromigration lifetime of the HBT by eliminating the fast diffusion path along the wire top surface which would be in contact with the dielectric copper cap layer, allows for tighter pitch layout and the elimination of staggered M1 and M2 wiring, while minimizing Time-Dependent Dielectric Breakdown. The structure of FIG. 3 is polished using, for example, a chemical mechanical polishing (CMP), and brush cleaned.

FIG. 4 shows a beginning structure in accordance with another aspect of the invention. Similar to FIG. 1, the structure 10 includes an HBT region comprising a collector 14, SiGe base 16 and emitter 18, formed on a substrate 12. Wiring structures 24 a are formed in a layer of dielectric 22, and are electrically connected to the collector 14 of the HBT. Wiring structures 24 b are formed in the dielectric 22, and are electrically connected to the SiGe base 16 of the HBT. A wiring structure 24 c is also formed in the dielectric 22, and is electrically connected to the emitter 18 of the HBT. In embodiments, the wiring structures 24 a, 24 b and 24 c can be, for example, tungsten or titanium nitride lined tungsten stud contacts.

Still referring to FIG. 4, a damascene wiring layer 26 is formed in another layer of the dielectric 22, and is electrically connected to each of the wiring structures 24 a, 24 b and 24 c. In embodiments, the wiring layer 26 can be, for example, TaN lined copper. The wiring layer 26 may be, for example, about 190 nm in height; although other dimensions are also contemplated by the invention. For example, the height of the wiring layer 26 may be 190 nm+/−20%.

The structure 10 further includes a conventional field effect transistor (FET) 20 having a dedicated wiring structure 24 d electrically connected thereto. The wiring structure 24 d is also electrically connected to a wiring layer 28. The wiring structure 24 d can be, for example, tungsten or titanium nitride lined tungsten stud contacts, and the wiring layer 28 can be TaN lined copper. The wiring layer 28 may be, for example, about 190 nm in height; although other dimensions are also contemplated by the invention. For example, the height of the wiring layer 28 may be about 190 nm+/−20%.

Still referring to FIG. 4, a masking layer 36 is deposited on the structure. In embodiments, the masking layer 36 can be, for example, SiCN which is deposited using conventional PECVD deposition processes preceded by an ammonia plasma copper surface treatment, or a self-aligned copper silicide surface treatment, as known in the art. In embodiments, the height of the masking layer is about 35 nm; although, other dimensions are also contemplated by the invention such as, for example, 25 nm. The masking layer 34 is patterned using conventional lithographic and etching processes to form an opening 36 over the HBT region. That is, the opening 36 exposes a top portion of the wiring layer 26, while protecting the FET (and more particularly protecting the wiring layer 28). The exposed surface can be stripped of photoresist using a non-oxygen containing plasma as discussed supra (e.g., an oxygen free environment so as to not corrode the exposed copper) and cleaned using, for example, a 100:1 dilute HF acid solution to prepare the surface for subsequent processing steps.

As shown in FIG. 5, a metal layer 38 is selectively deposited on the exposed copper wiring layer 26. In embodiments, the metal layer 38 is CoWP or other metal that is selectively plated to copper. Alternatively, the metal layer 38 could be selectively deposited using a CVD process and could consist of Sn, In, or W. The metal layer 38 is about 25 nm in height; although, other dimensions are also contemplated by the present invention. In embodiments, the metal layer 38 selectively increases electromigration lifetime of the HBT by eliminating the fast diffusion path along the copper surface, allows for tighter pitch layout and the elimination of staggered M1 and M2 wiring, while minimizing Time-Dependent Dielectric Breakdown.

In an alternative embodiment, a layer of Sn can be deposited on the structure of FIG. 4 (e.g., over the wiring layer 26 and spaces therebetween). The Sn can be annealed at high temperature (e.g., about above 800° C.) to form a CuSn alloy and unreacted Sn can be removed by a wet etching process (e.g., Sn on the dielectric). In this way, remaining Sn (as represented by metal layer 38 of FIG. 5) will remain on the wiring layer 26. The structure can then be cleaned in a conventional manner. In any embodiment, the relaxed spacing rules used inside the window (HBT region) will eliminate TDDB or yield issues. Although only one copper wiring level (M1) is shown with the local capping layer, additional layers of wires could be locally capped; or only levels above the first copper wiring level (M1) could be capped (e.g. M2, M7, etc.).

FIG. 6 shows a graph comparing peak fT to peak Jc. In the graph of FIG. 6, the y-axis represents peak frequency (fT) in GHz and the x-axis represents current (Jc) in mA/um². As can be seen, the trend in more recent generations of SiGe technologies is to increase the peak frequency while increasing the required current density. In the present invention, the HBT peak current density is 25 mA/μm² (compared to conventional wires which have a peak current density of under 8 mA/μm²). The present invention is advantageously able to achieve about 25 mA/μm² without increasing the wiring dimensions, or affecting other wiring layers.

FIG. 7 shows a block diagram of an exemplary design flow 900 used for example, in semiconductor IC logic design, simulation, test, layout, and manufacture. Design flow 900 includes processes, machines and/or mechanisms for processing design structures or devices to generate logically or otherwise functionally equivalent representations of the design structures and/or devices described above and shown in FIGS. 3 and 5, for example. The design structures processed and/or generated by design flow 900 may be encoded on machine-readable transmission or storage media to include data and/or instructions that when executed or otherwise processed on a data processing system generate a logically, structurally, mechanically, or otherwise functionally equivalent representation of hardware components, circuits, devices, or systems. Machines include, but are not limited to, any machine used in an IC design process, such as designing, manufacturing, or simulating a circuit, component, device, or system. For example, machines may include: lithography machines, machines and/or equipment for generating masks (e.g. e-beam writers), computers or equipment for simulating design structures, any apparatus used in the manufacturing or test process, or any machines for programming functionally equivalent representations of the design structures into any medium (e.g. a machine for programming a programmable gate array).

Design flow 900 may vary depending on the type of representation being designed. For example, a design flow 900 for building an application specific IC (ASIC) may differ from a design flow 900 for designing a standard component or from a design flow 900 for instantiating the design into a programmable array, for example a programmable gate array (PGA) or a field programmable gate array (FPGA) offered by Altera® Inc. or Xilinx® Inc.

FIG. 7 illustrates multiple such design structures including an input design structure 920 that is preferably processed by a design process 910. Design structure 920 may be a logical simulation design structure generated and processed by design process 910 to produce a logically equivalent functional representation of a hardware device. Design structure 920 may also or alternatively comprise data and/or program instructions that when processed by design process 910, generate a functional representation of the physical structure of a hardware device. Whether representing functional and/or structural design features, design structure 920 may be generated using electronic computer-aided design (ECAD) such as implemented by a core developer/designer. When encoded on a machine-readable data transmission, gate array, or storage medium, design structure 920 may be accessed and processed by one or more hardware and/or software modules within design process 910 to simulate or otherwise functionally represent an electronic component, circuit, electronic or logic module, apparatus, device, or system such as those shown in FIGS. 3 and 5, for example. As such, design structure 920 may comprise files or other data structures including human and/or machine-readable source code, compiled structures, and computer-executable code structures that when processed by a design or simulation data processing system, functionally simulate or otherwise represent circuits or other levels of hardware logic design. Such data structures may include hardware-description language (HDL) design entities or other data structures conforming to and/or compatible with lower-level HDL design languages such as Verilog and VHDL, and/or higher level design languages such as C or C++.

Design process 910 preferably employs and incorporates hardware and/or software modules for synthesizing, translating, or otherwise processing a design/simulation functional equivalent of the components, circuits, devices, or logic structures shown in FIGS. 3 and 5, for example, to generate a netlist 980 which may contain design structures such as design structure 920. Netlist 980 may comprise, for example, compiled or otherwise processed data structures representing a list of wires, discrete components, logic gates, control circuits, I/O devices, models, etc. that describes the connections to other elements and circuits in an integrated circuit design. Netlist 980 may be synthesized using an iterative process in which netlist 980 is resynthesized one or more times depending on design specifications and parameters for the device. As with other design structure types described herein, netlist 980 may be recorded on a machine-readable data storage medium or programmed into a programmable gate array. The medium may be a non-volatile storage medium such as a magnetic or optical disk drive, a programmable gate array, a compact flash, or other flash memory. Additionally, or in the alternative, the medium may be a system or cache memory, buffer space, or electrically or optically conductive devices and materials on which data packets may be transmitted and intermediately stored via the Internet, or other networking suitable means.

Design process 910 may include hardware and software modules for processing a variety of input data structure types including netlist 980. Such data structure types may reside, for example, within library elements 930 and include a set of commonly used elements, circuits, and devices, including models, layouts, and symbolic representations, for a given manufacturing technology (e.g., different technology nodes, 32 nm, 45 nm, 90 nm, etc.). The data structure types may further include design specifications 940, characterization data 950, verification data 960, design rules 970, and test data files 985 which may include input test patterns, output test results, and other testing information. Design process 910 may further include, for example, standard mechanical design processes such as stress analysis, thermal analysis, mechanical event simulation, process simulation for operations such as casting, molding, and die press forming, etc. One of ordinary skill in the art of mechanical design can appreciate the extent of possible mechanical design tools and applications used in design process 910 without deviating from the scope and spirit of the invention. Design process 910 may also include modules for performing standard circuit design processes such as timing analysis, verification, design rule checking, place and route operations, etc.

Design process 910 employs and incorporates logic and physical design tools such as HDL compilers and simulation model build tools to process design structure 920 together with some or all of the depicted supporting data structures along with any additional mechanical design or data (if applicable), to generate a second design structure 990. Design structure 990 resides on a storage medium or programmable gate array in a data format used for the exchange of data of mechanical devices and structures (e.g. information stored in a IGES, DXF, Parasolid XT, JT, DRG, or any other suitable format for storing or rendering such mechanical design structures). Similar to design structure 920, design structure 990 preferably comprises one or more files, data structures, or other computer-encoded data or instructions that reside on transmission or data storage media and that when processed by an ECAD system generate a logically or otherwise functionally equivalent form of one or more of the embodiments of the invention shown in FIGS. 3 and 5, for example. In one embodiment, design structure 990 may comprise a compiled, executable HDL simulation model that functionally simulates the devices shown in FIGS. 3 and 5, for example.

Design structure 990 may also employ a data format used for the exchange of layout data of integrated circuits and/or symbolic data format (e.g. information stored in a GDSII (GDS2), GL1, OASIS, map files, or any other suitable format for storing such design data structures). Design structure 990 may comprise information such as, for example, symbolic data, map files, test data files, design content files, manufacturing data, layout parameters, wires, levels of metal, vias, shapes, data for routing through the manufacturing line, and any other data required by a manufacturer or other designer/developer to produce a device or structure as described above and shown in FIGS. 3 and 5, for example. Design structure 990 may then proceed to a stage 995 where, for example, design structure 990: proceeds to tape-out, is released to manufacturing, is released to a mask house, is sent to another design house, is sent back to the customer, etc.

The method as described above is used in the fabrication of integrated circuit chips. The resulting integrated circuit chips can be distributed by the fabricator in raw wafer form (that is, as a single wafer that has multiple unpackaged chips), as a bare die, or in a packaged form. In the latter case the chip is mounted in a single chip package (such as a plastic carrier, with leads that are affixed to a motherboard or other higher level carrier) or in a multichip package (such as a ceramic carrier that has either or both surface interconnections or buried interconnections). In any case the chip is then integrated with other chips, discrete circuit elements, and/or other signal processing devices as part of either (a) an intermediate product, such as a motherboard, or (b) an end product. The end product can be any product that includes integrated circuit chips, ranging from toys and other low-end applications to advanced computer products having a display, a keyboard or other input device, and a central processor.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises” and/or “comprising,” when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

The corresponding structures, materials, acts, and equivalents of all means or step plus function elements in the claims below, where applicable, are intended to include any structure, material, or act for performing the function in combination with other claimed elements as specifically claimed. The description of the present invention has been presented for purposes of illustration and description, but is not intended to be exhaustive or limited to the invention in the form disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the invention. The embodiment was chosen and described in order to best explain the principles of the invention and the practical application, and to enable others of ordinary skill in the art to understand the invention for various embodiments with various modifications as are suited to the particular use contemplated. Accordingly, while the invention has been described in terms of embodiments, those of skill in the art will recognize that the invention can be practiced with modifications and in the spirit and scope of the appended claims. 

1. A method of forming two devices connected by metal wires on a same wiring level, the metal wire of a first of the two devices being formed by selectively forming a metal cap layer on copper wiring structures, while blocking the formation of the metal cap layer on a second of the two devices.
 2. The method of claim 1, wherein the copper wiring structures are formed electrically connected to an emitter, collector and base of a heterojuncture bipolar transistor.
 3. The method of claim 1, wherein the metal cap layer is CoWP which is selectively deposited on the copper wiring structures.
 4. The method of claim 1, wherein the metal cap layer is TaN or TiN deposited in trenches etched into the copper wiring structures.
 5. The method of claim 2, wherein the selectively forming comprises etching the copper wiring structures to form trenches and selectively depositing the metal cap layer in the trenches.
 6. The method of claim 5, further comprising masking a copper wiring structure of a field effect transistor (FET) during the selectively depositing the metal cap layer in the trenches.
 7. The method of claim 2, further comprising protecting a copper cap layer of an adjacent FET with a mask, wherein the selectively forming the metal cap layer includes depositing CoWP selectively only on the copper wiring structures.
 8. The method of claim 2, further comprising: depositing a resist on the copper wiring structures and a copper layer of a FET; patterning the resist to expose a surface of the copper wiring structures, while the copper layer of the FET remains masked by the resist; and forming a trench in the copper wiring structures, wherein the selectively forming the metal cap layer on the copper wiring structures includes depositing metal in the trenches.
 9. The method of claim 2, further comprising: depositing a masking layer of SiCN on the copper wiring structures and copper cap layer of a FET; patterning the masking layer to expose the copper wiring structures, wherein the resist remains on the copper cap layer of the FET; and the selectively forming the metal cap layer includes depositing a selective metal on the exposed copper wiring structures.
 10. The method of claim 9, further comprising stripping the exposed copper wiring structures with Dilute Hydrofluoric Acid (DHF) in an oxygen free environment so as to not corrode the exposed copper wiring structures.
 11. The method of claim 1, wherein the selectively depositing comprises: depositing a layer of Sn on the metal cap layer and spaces therebetween; annealing the Sn layer; and removing unreacted Sn on the spaces by a wet etching process to selectively form the metal cap layer on the copper wiring structures.
 12. The method of claim 1, wherein the selectively depositing comprises providing a mask over the metal cap layer on the second of the two devices, and depositing the metal cap layer on the copper wiring structures.
 13. The method of claim 12, wherein the providing the mask comprising providing a mask over the metal cap layer on the second of the two devices and the metal cap layer on the copper wiring structures, and removing the mask over the metal cap layer, prior to the depositing.
 14. The method of claim 13, wherein the mask is a photoresist layer which is removed over the metal cap layer.
 15. The method of claim 14, wherein the copper wiring structures are etched Using dilute sulfuric acid/hydrogen peroxide (DSP) solution to form a trench.
 16. The method of claim 15, wherein the trench is approximately 40 nm+/−10% in depth.
 17. The method of claim 16, wherein the metal cap layer is one of TaN, TaN/Ta, Ru, W, Mn, or TiN, deposited to a height of about 60 nm.
 18. The method of claim 1, further comprising depositing a masking layer of SiCN over the metal wire and the copper wiring structures, and patterning the masking layer to expose the copper wiring structures.
 19. The method of claim 18, wherein the metal cap layer is selectively deposited only on the exposed copper wiring structures. 